The present invention relates to a logic circuit, and in particular to a high speed logic circuit using semiconductor devices, each having a device structure making the best use of characteristics of a hetero-junction bipolar transistor.
Owing to recent progress in the MBE (Molecular Beam Epitaxy) and the MOCVD (Metal Organic Chemical Vapor Deposition) technology, crystal growth can be effected with controllability at atomic level.
A hetero-junction bipolar transistor (HBT) having a new structure making use of two-dimensional charge carriers at a semiconductor hetero-junction interface formed by the technologies described above is disclosed in JP-A-Sho 62-199079, in which it is shown that a bipolar transistor (BJT) using two-dimensional charge carriers (or an inversion layer, a storage layer) at a semiconductor hetero-junction interface as a base layer and an electric field transistor (FET) using a bipolar transistor (BJT) as an active layer can be formed in a same substrate, making it possible to realize a circuit, where there exist BJTs and FETs mixedly.
As a technology, by which BJTs and FETs are used mixedly, e.g. the BiCMOS technology is well known, by which an Si BJT and a CMOS (complementary type metal-oxide-semiconductor) FET are formed simultaneously. Consequently, even with a BJT using a hetero-junction and an FET, from the point of view of circuit construction, it is relatively easy to realize a circuit similar to the BiCMOS. However such a circuit is formed merely by diverting almost a basis prior art circuit and it cannot be said that it makes the best use of the crystal growth technology having the controllability at atomic level and the device structure using it.
On the other hand there is known the IIL (Integrated Injection Logic) circuit as an SiBJT, for which high density integration is possible and which can be fabricated by a simple fabrication process. In the IIL circuit, a one-gate circuit can be realized with almost one transistor while reducing the area of the circuit owing to a construction, in which an npn type transistor of inversely-biased operation and a horizontal pnp type transistor are combined. FIG. 14A is a cross-sectional view showing a basic construction of a prior art IIL circuit and FIG. 14B is an equivalent circuit diagram thereof.
The IIL circuit is constructed, as indicated in FIG. 14A, by forming p-type regions 102 and 103 in an n-type substrate 101 by using the diffusion or ion implantation technology and further by forming an n-type region 104 and this circuit can be represented by the equivalent circuit as indicated in FIG. 14B. An npn type transistor 106 effecting a logic operation is realized by a vertical transistor of inversely-biased operation, the n-type region 101, the p-type region 102 and the n-type region 104 serving as an emitter, a base and a collector, respectively. The emitter of the vertical transistor, i.e. substrate, is grounded. On the other hand, a pnp type transistor 107 acting as an injector has the p-type region 102 as the collector in common with the base region of the transistor 106 and the n-type substrate 101 as the base in common with the emitter region of the transistor 106. The p-type region 103 serves as the emitter thereof.
The operation of this circuit is realized by two states, in which the pnp type transistor 107 supplies injector current to the base of the transistor 106 or to the preceding gate circuit. That is, when the preceding gate circuit is in a state where no current flows therethrough (hereinbelow called OFF state), since the injector current flows to the base of the transistor 106, a state is established where current flows through the transistor 106 (hereinbelow called ON state). Therefore output terminals Vout 1 and Vout 2 pull-in current from the succeeding gate circuit so that potentials thereof are close to the ground potential. On the contrary, when the transistor in the preceding gate circuit is in the ON state, since the injector current is drawn by the collector in the preceding gate circuit, the transistor 106 is in the OFF state so that the potentials of the output terminals Vout 1 and Vout 2 are at a logic high level, i.e. higher than the ground potential by the base-emitter voltage of the transistor in the succeeding stage.
The IIL circuit is fabricated by the diffusion or ion implantation technology. N or p-type layers are formed while effecting impurities compensation so that the higher the layer is, in other words the later the fabrication step is, the higher the concentration of impurities is, with which the layer is doped. As the result, in the pn junction formed by the emitter (presumed to be n-type), which is the uppermost layer, and the base (presumed to be p-type), which is directly below it, electrons injected from the emitter to the base are much more abundant than holes injected from the base to the emitter. For this reason, base current is small and current gain is great. Similarly, in the base-collector junction, holes injected from the base to the collector are much more abundant than electrons injected from the collector to the base. This means that the current gain is small at the inversely-biased operation, in which the collector acts as the emitter. This means further that the amount of holes stored in the collector increases in the saturation region, i.e. in the operation region where the base-collector junction is forward-biased, in the usual forward-biased operation. Consequently, the IIL circuit using a transistor of inversely-biased operation with the collector on the upside has a drawback that, since the cut-off frequency cannot be raised and in addition the current gain is low, a great amount of minority carriers (holes) are stored in the substrate acting as the emitter and the working speed is low.
Therefore various sorts of IIL type circuits improved at this point have been proposed. A circuit disclosed e.g. in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14 No. 3, JUNE 1979, pp. 585-590, called ISL (Integrated Schottky Logic), is indicated in FIGS. 15A and 15B. FIG. 15A shows the device structure of the ISL circuit and FIG. 15B shows the equivalent circuit thereof.
As indicated in FIG. 15A, the npn type transistor 117 effecting logic operation in the ISL circuit has a vertical structure, in which the emitter, the base and the collector are realized by the n-type region 111, the p-type region 112 and the n-type region 113, respectively. In FIG. 15B, Schottky diodes 119 connected with the output terminals Vout 1 and Vout 2 are realized by forming Schottky electrodes 116 on an n-type region 113a. The pnp type transistor 118 has a structure combined with the transistor 117, in which the p-type region 112, the n-type region 113 and the p-type region 114 or 115 serve as the emitter, the base and the collector, respectively. An injector 120 is formed separately by resistors, etc., differently from the IIL circuit, although it is not indicated in FIG. 15A. What is intended to be improved by this circuit with respect to the IIL circuit is following two points; that (1) the inversely-biased operation of the transistor is abandoned and the transistor is used in the forward-biased operation and that (2) lowering in the working speed due to the fact that the working point enters the saturation region when the transistor is turned-on so that minority carriers are stored therein is avoided. In order to realize the first point, it is necessary to separate the output terminals from each other. For this purpose the Schottky diodes 119 described above are formed. In order to realize the second point, there is a method, by which clamping means is added so that the collector potential of the transistor 117 is not lowered excessively. In FIG. 15B the pnp type transistor 118 constitutes this clamping means, which makes holes, which are minority carriers stored in the collector, flow from the region 113 to 114 or 115 owing to the operation of the transistor 118, when the transistor 117 is in the ON state, so as to prevent the storage of the minority carriers.
The logic circuit such as the ISL circuit described above, etc., improved type of the IIL circuit, is better than the IIL in the circuit speed, etc., because a vertical transistor of forward-biased operation is used, but it is realized at the cost of some characteristics, which the original IIL circuit has. For example, in the ISL circuit, an element isolation region is required similarly to the case where a usual BJT is used, while no element isolation region is required in the ISL circuit, etc., because the emitter of the transistor of inversely-biased operation is the n-type substrate, which can be used at the same time for other transistors, and therefore it is difficult to increase the degree of integration. In addition, Schottky diodes are required for isolating a plurality of outputs and further clamping means is necessary for preventing the storage of minority carriers due to the saturation of the transistors, which makes the construction complicated. Furthermore, even if the clamping means is disposed, it is impossible to prevent completely the storage of minority carriers. Therefore there were problems that increase in the speed was limited, etc.